1. Field of the Invention
The present invention relates generally to voltage generation circuits generating a predetermined voltage and, particularly to a voltage generation circuit provided with at least a detecting circuit, a charge pump circuit and a clamping circuit.
2. Description of the Background Art
In a semiconductor integrated circuit device, a voltage generation circuit is provided for generating an internal voltage such as a boosted voltage V.sub.PP and a substrate voltage V.sub.BB.
FIG. 7 is a circuit diagram of a boosted voltage generation circuit as an example of a conventional voltage generation circuit. Referring to FIG. 7, the voltage generation circuit includes a detecting circuit 10, a ring oscillator 2, a charge pump circuit 3 and a clamping circuit 400. A power supply node N1 receives a power supply voltage V.sub.CC. A ground node N2 receives a ground voltage. An output node N3 receives and outputs a boosted voltage V.sub.PP which is an output voltage from charge pump circuit 3.
Detecting circuit 10 includes P channel transistors 11 and 12, an N channel transistor 13 and an inverter 14.
Transistors 11, 12 and 13 are connected in series between output node N3 and ground node N2. Transistor 11 has its gate connected to a node between transistors 11 and 12. Respective gates of transistors 12 and 13 are connected to power supply node N1. A node N10 between transistors 12 and 13 is connected through inverter 14 to one input node of an NAND gate 21 in ring oscillator 2, which will be described later.
Ring oscillator 2 includes NAND gate 21 and inverters 22, 23 and 24. NAND gate 21 and inverters 22, 23 and 24 are connected in series between inverter 14 in detecting circuit 10 and an inverter 31 in charge pump circuit 3, which will be described later. A node between inverters 23 and 24 is connected to the other input node of NAND gate 21.
Charge pump circuit 3 includes inverters 31 and 32, a capacitor 33, and N channel transistors 34 and 35. Between inverter 24 in ring oscillator 2 and output node N3, inverters 31 and 32, capacitor 33 and transistor 35 are connected in series. Transistor 35 has its gate connected to a node N30 between capacitor 33 and transistor 35.
Between power supply node N1 and the node between capacitor 33 and transistor 35, transistor 34 is connected. Transistor 34 has its gate connected to power supply node N1.
Clamping circuit 400 includes a group of transistors 410 provided between output node N3 and ground node N2. Group of transistors 410 includes six P channel transistors 41. These transistors 41 are connected in series between output node N3 and ground node N2.
In the group of transistors 410, a transistor 41 connected to ground node N2 has its gate connected to ground node N2. Each of the remaining transistors 41 has its gate connected to each node between that transistor 41 itself and an adjacent transistor 41 at the side of ground node N2.
The operation of this voltage generation circuit will be described.
At first, the operation of detecting circuit 10 will be described. In detecting circuit 10, a detection level is set based on a power supply voltage V.sub.CC and threshold voltages V.sub.TH of respective transistors 11 and 12. The detection level is a reference voltage for detection as to whether the boosted voltage V.sub.PP has exceeded a predetermined value. The detection level is, specifically, V.sub.CC +2.vertline.V.sub.TH .vertline.. In detecting circuit 10, transistor 13 is normally in on-state.
When the boosted voltage V.sub.PP is not higher than the detection level, both of transistors 11 and 12 are turned off. In this case, a logic level of node N10 attain a low level. As a result, a logic level of an output signal from inverter 14 attains a high level.
In contrast, when the boosted voltage V.sub.PP is higher than the detection level, both of-transistors 11 and 12 are turned on. In this case, the logic level of node N10 attains a high level. As a result, the logic level of the output signal from inverter 14 attains a low level.
Therefore an output signal from detecting circuit 10 attains a high level when the boosted voltage V.sub.PP is not higher than the detection level, and attains a low level when the boosted voltage V.sub.PP is higher than the detection level.
The operation of ring oscillator 2 will be described. When the output signal from detecting circuit 10 is at a high level, a logic level of an output signal of NAND gate 21 is inverted in a constant cycle owing to a loop circuit of NAND gate 21 and inverters 22 and 23. As a result, a logic level of an output signal from inverter 24 is inverted in a constant cycle.
On the other hand, when the output signal from detecting circuit 10 is at a low level, the output of NAND gate 21 is fixed to a high level. As a result, the logic level of the output signal from inverter 24 is fixed to a low level.
Therefore, the output signal of ring oscillator 2 becomes a pulse signal in which a logic level is inverted in a constant cycle when the output signal from detecting circuit 10 is at a high level, and becomes a signal which is fixed to a low level when the output signal from detecting circuit 10 is at a low level.
The operation of charge pump circuit 3 will be described. When the output signal of ring oscillator 2 is the pulse signal described above, it operates as follows.
When the output signal from ring oscillator 2 falls from a high level to a low level, the output signal is applied to capacitor 33 through inverters 31 and 32. Thus, the voltage of node N30 drops because of a capacitive coupling of capacitor 33.
Due to the voltage drop, the voltage of node N30 becomes lower than the voltage which is lower than the power supply voltage V.sub.CC by a threshold voltage V.sub.TH of transistor 34. Thus, transistor 34 is turned on resulting a voltage of node N30 being V.sub.CC -V.sub.TH.
When the output signal of ring oscillator 2 rises from a low level to a high level, the output signal is applied to capacitor 33 through inverters 31 and 32. Thus, the voltage of node N30 rises because of the capacitive coupling of capacitor 33.
Due to the voltage rise, the voltage of node N30 rises by the power supply voltage V.sub.CC. As a result, the voltage of node N30 attains 2V.sub.CC -V.sub.TH. In this state, transistor 35 is turned on. As a result, the boosted voltage V.sub.PP which is a voltage of output node N3 becomes lower than the voltage of node N30 by a threshold value V.sub.TH of transistor 35, that is, 2V.sub.CC -2V.sub.TH.
Therefore, when a pulse signal is applied to charge pump circuit 3, charge pump circuit 3 operates to rise the boosted voltage V.sub.PP. On the other hand, when a signal applied to charge pump circuit 3 is fixed to a low level, charge pump circuit 3 does not operate to rise the boosted voltage V.sub.PP.
The operation of clamping circuit 400 will be described. In clamping circuit 400, a clamp level is set according to the total value of threshold voltages V.sub.TH of respective transistors 41 in group of transistors 410. The clamp level is a reference voltage for clamping the boosted voltage V.sub.PP at a constant value when the boosted voltage V.sub.PP becomes higher than a predetermined value. Specifically, the clamp level is a voltage which is higher than a ground voltage by the total value of threshold voltages V.sub.TH of the transistors 41.
In clamping circuit 400, when the voltage of output node N3, i.e., the boosted voltage V.sub.PP exceeds the clamp level, each transistor 41 in group of transistors 410 is turned on to discharge output node N3 to clamp the boosted voltage V.sub.PP at the clamp level.
Summary of the operation of the voltage generation circuit described above is as follows.
When the boosted voltage V.sub.PP is lower than the detection level, a control signal is applied to charge pump circuit 3 through ring oscillator 2 from detecting circuit 10, and charge pump circuit 3 operates to rise the boosted voltage V.sub.PP. On the other hand, when the boosted voltage V.sub.PP is higher than the clamp level, clamping circuit 400 operates to clamp the boosted voltage V.sub.PP at the clamp level.
Relation of the detection level and the clamp level will be described. FIG. 8 is a graph showing the relation of the detection level and the clamp level. In FIG. 8, the ordinate indicates the boosted voltage V.sub.PP and the abscissa indicates the power supply voltage V.sub.CC. The detection level is indicated as a solid line and the clamp level is indicated as a broken line.
Referring to FIG. 8, since the detection level is set based on the power supply voltage V.sub.CC and threshold voltages V.sub.TH of transistors 11 and 12, it rises as the power supply voltage V.sub.CC rises. On the other hand, since the clamp level is set based on the total value of the threshold voltages V.sub.TH of transistors 41 in group of transistors 410, it is constant independent of the power supply voltage V.sub.CC.
Hence, when the detection level is set lower than the clamp level, charge pump circuit 3 and clamping circuit 400 do not operate at the same time in the voltage generation circuit, and normal operation is carried out.
However, there are cases where the detection level is set higher than the clamp level according to the rise of the power supply voltage V.sub.CC shown in FIG. 8. In such cases, charge pump circuit 3 may possibly operate for boosting even though clamping circuit 400 is in operation for clamping. That is, clamping circuit 400 and charge pump circuit 3 operate at the same time.
Thus, in a conventional voltage generation circuit, there may be a case where the clamping circuit and charge pump circuit 3 operate at the same time, which causes unnecessary power consumption, resulting in the increase of power consumption.